header banner
Default

Users of Ryzen 7000X3D CPUs Can Adjust CCDs with Fine Grained Control Thanks to an ASUS BIOS Update


Table of Contents

    raphael x3d

    When AMD first announced the Ryzen 7000 processors with 3D V-Cache, we noted that the boost clocks on the Ryzen 9 7900X3D and Ryzen 9 7950X3D were the same as their non-X3D siblings. It turned out that this is possible because only one of the two CCDs under the IHS actually gets 3D V-Cache applied; the other one is free to boost to the full turbo clock.

    amd socket am5 cpus chart

    While this asymmetrical configuration seems like it would be a hassle for end-users, AMD assured us that it had already worked with Microsoft to make sure Windows understands the difference in the two CCDs and thus can schedule tasks accordingly. That's all well and good, but as we all know, "intelligent" software often isn't. Thankfully, it seems like users with one of these CPUs will be able to configure the algorithm manually in firmware.


    That information comes to us by way of famed leaker HXL (@9550pro on Twitter), who posted a couple of screenshots of an ASUS X670 motherboard's beta BIOS that adds a menu called "Core Flex." This menu is clearly intended for the Ryzen 9 79xx X3D processors that have multiple CCDs and 3D V-Cache, as it allows you to configure when the processor will swap a task from one CCD to the other.

    core flex menu

    Image: HXL

    Interestingly, since this is configured in firmware, it seems to be "OS / driver agnostic," meaning it will work in Linux as well as older versions of Windows. It seems like there are multiple "algorithms" that can be configured, and users appear to be able to select from a variety of conditions under which the scheduler will move a task from one CCD to the other.

    core flex menu 2

    Image: HXL

    Those conditions appear to include at least core current and memory activity, both of which make sense—a task with heavy memory activity will want to be on the V-Cache CCD, while a task with intense compute activity will want to be on the higher-clocked non-V-Cache CCD.

    core flex algorithm explanation

    Image: HXL

    While we're very pleased to see that these controls exist—your author in particular is fond of anything that increases user agency—we do hope that it won't be necessary for end-users to manipulate this menu most of the time. As we noted above, AMD says it has already worked with Microsoft to make sure apps get scheduled in the correct place. We'll find out how well they did when the chips hit at the end of this month, less than a week from now.

    Sources


    Article information

    Author: Theresa Hardy

    Last Updated: 1704619561

    Views: 937

    Rating: 4.4 / 5 (40 voted)

    Reviews: 87% of readers found this page helpful

    Author information

    Name: Theresa Hardy

    Birthday: 1923-10-20

    Address: 444 George Villages, Brewerchester, IL 26757

    Phone: +4284000691501986

    Job: Quantum Physicist

    Hobby: Fencing, Running, Traveling, Bird Watching, Bird Watching, Card Games, Photography

    Introduction: My name is Theresa Hardy, I am a capable, exquisite, Gifted, rare, unswerving, accessible, ingenious person who loves writing and wants to share my knowledge and understanding with you.